作业帮懂verilog HDL语言的来大家帮我看看这个三八译码器的程序,帮我找找哪里错了~module 38(A,B);input [2:0] A;output [7:0] B;reg [7:0] B;always@(B)begin case (a)3'b000:B = 8'b00000001;3'b001:B = 8'b00000010;3'b010:B = 8'b00000100;3
来源：学生作业帮助网 编辑：作业帮 时间：2024/05/01 05:24:02
![懂verilog HDL语言的来大家帮我看看这个三八译码器的程序,帮我找找哪里错了~module 38(A,B);input [2:0] A;output [7:0] B;reg [7:0] B;always@(B)begin case (a)3'b000:B = 8'b00000001;3'b001:B = 8'b00000010;3'b010:B = 8'b00000100;3](/uploads/image/z/1747001-65-1.jpg?t=%E6%87%82verilog+HDL%E8%AF%AD%E8%A8%80%E7%9A%84%E6%9D%A5%E5%A4%A7%E5%AE%B6%E5%B8%AE%E6%88%91%E7%9C%8B%E7%9C%8B%E8%BF%99%E4%B8%AA%E4%B8%89%E5%85%AB%E8%AF%91%E7%A0%81%E5%99%A8%E7%9A%84%E7%A8%8B%E5%BA%8F%2C%E5%B8%AE%E6%88%91%E6%89%BE%E6%89%BE%E5%93%AA%E9%87%8C%E9%94%99%E4%BA%86%7Emodule+38%28A%2CB%29%3Binput+%5B2%3A0%5D+A%3Boutput+%5B7%3A0%5D+B%3Breg+%5B7%3A0%5D+B%3Balways%40%28B%29begin+case+%28a%293%27b000%3AB+%3D+8%27b00000001%3B3%27b001%3AB+%3D+8%27b00000010%3B3%27b010%3AB+%3D+8%27b00000100%3B3)
懂verilog HDL语言的来大家帮我看看这个三八译码器的程序,帮我找找哪里错了~module 38(A,B);input [2:0] A;output [7:0] B;reg [7:0] B;always@(B)begin case (a)3'b000:B = 8'b00000001;3'b001:B = 8'b00000010;3'b010:B = 8'b00000100;3
懂verilog HDL语言的来
大家帮我看看这个三八译码器的程序,帮我找找哪里错了~
module 38(A,B);
input [2:0] A;
output [7:0] B;
reg [7:0] B;
always@(B)
begin
case (a)
3'b000:B = 8'b00000001;
3'b001:B = 8'b00000010;
3'b010:B = 8'b00000100;
3'b011:B = 8'b00001000;
3'b100:B = 8'b00010000;
3'b101:B = 8'b00100000;
3'b110:B = 8'b01000000;
3'b111:B = 8'b10000000;
endcase
end
endmodule
懂verilog HDL语言的来大家帮我看看这个三八译码器的程序,帮我找找哪里错了~module 38(A,B);input [2:0] A;output [7:0] B;reg [7:0] B;always@(B)begin case (a)3'b000:B = 8'b00000001;3'b001:B = 8'b00000010;3'b010:B = 8'b00000100;3
module my_38(A,B);
input [2:0] A;
output [7:0] B;
reg [7:0] B;
always@(A)
begin
case (A)
3'b000:B = 8'b00000001;
3'b001:B = 8'b00000010;
3'b010:B = 8'b00000100;
3'b011:B = 8'b00001000;
3'b100:B = 8'b00010000;
3'b101:B = 8'b00100000;
3'b110:B = 8'b01000000;
3'b111:B = 8'b10000000;
endcase
end
endmodule
该成这样就OK了,原因是模块明必须以字母开头,你要做的是38译码所以always的敏感列表要该成A,case中的a是没用定义的变量Verilog是大小写敏感的也就是大写和小写是不同的变量你这里只有A所以把a改成A.