作业帮一个vhdl的语句,一直报错显示width mismatch in relational operator,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY tlc IS PORT (clk,emerge:IN STD_LOGIC; ra,rb,ya,yb,ga,gb:out std_logic);END;ARCHITECTURE bhv
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一个vhdl的语句,一直报错显示width mismatch in relational operator,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY tlc IS PORT (clk,emerge:IN STD_LOGIC; ra,rb,ya,yb,ga,gb:out std_logic);END;ARCHITECTURE bhv
一个vhdl的语句,一直报错显示width mismatch in relational operator,
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
ENTITY tlc IS
PORT (clk,emerge:IN STD_LOGIC;
ra,rb,ya,yb,ga,gb:out std_logic);
END;
ARCHITECTURE bhv OF tlc IS
type state is (rg,ry,gr,yr,rr);
constant timemax:integer :=45;
constant time_rg:integer :=30;
constant time_ry:integer :=5;
constant time_gr:integer :=45;
constant time_yr:integer :=5;
signal state_next:state;
signal state_curr:state;
signal times :integer range 0 to timemax;
BEGIN
p1:\x05process(clk,emerge)
variable cnt:integer range 0 to timemax;
begin
\x05\x05if (emerge='1')then
state_curr
一个vhdl的语句,一直报错显示width mismatch in relational operator,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY tlc IS PORT (clk,emerge:IN STD_LOGIC; ra,rb,ya,yb,ga,gb:out std_logic);END;ARCHITECTURE bhv
我将上述描述在Quartus II 8.0下编译后没有出现报错,只有几个警告.